The memory cell provided in a nonvolatile semiconductor memory device such as a NAND flash memory has a stacked gate structure in which a floating gate and a control gate are stacked via an intergate insulating film.
Here, with the progress of miniaturization, the dimension between the adjacent floating gates is reduced. The parasitic capacitance occurring in this portion has a non-negligible influence on the operating characteristics of the nonvolatile semiconductor memory device.
In this context, a nonvolatile semiconductor memory device has been proposed in which a void portion is provided between the adjacent memory cells to reduce the parasitic capacitance occurring between the memory cells.
However, in the step of forming an insulating film above the control gate, penetration of insulator into the void portion cannot be suppressed.
This results in increasing the parasitic capacitance occurring between the memory cells, and may hamper the improvement in the operating characteristics of the nonvolatile semiconductor memory device.
Furthermore, the amount of insulator penetrating into the void portion is changed under the influence of variations in the shape of the memory cell and the dimension between the memory cells, and variations in the process for forming the insulating film. Hence, variations occur in the proportion occupied by the void portion between the memory cells. This may result in unstable operating characteristics of the nonvolatile semiconductor memory device.